This invention relates to a synchronous sigma-delta modulator for analog input signals comprising, in feedback arrangement, an integrating filter, a decision circuit for comparing output signals of the integrating filter with a reference level and for generating output pulses dependent on the result of the comparison at synchronously clocked instants, and means for feeding the output pulses of the decision circuit with the analog input signals to said integrating filter. Such synchronous sigma-delta modulators are well known in the art e.g. from the article "A Unity Bit Coding Method by Negative Feedback" by H. Inose et al. in "Proceedings of the IEEE" of November 1963, pp. 1524-1535, wherein the decision circuit is referred to as "pulse modulator".
Synchronous sigma-delta modulators are used as analog to digital converters in various signal processing applications. Because of the problems involved with higher frequencies, the practical use of these modulators has been substantially restricted to voice band and audio band applications. It is true, that the above mentioned article describes the use of synchronous sigma-delta modulators for the modulation of video signals, but therein the proposed sampling frequency at which the decision circuit is operated is not higher than 50 MHz, whereas sampling frequencies higher than 1 GHz are strongly preferred for high performance video applications (i.e. signal bandwidth&gt;5 MHz and signal to noise ratio&gt;60 db).
In practice the decision circuit is a clocked comparator, which has to perform a high-frequency non-linear operation on weak input signals and has to provide a sequence of identical return to zero pulses. If the pulses are not identical, noise is introduced in the modulator. With present day technology it is not well possible to design a decision switch which operates sufficiently noise free at the high clock-frequency needed. This is due to the fact that the decision switch is not sufficiently reset from the previous switching action. Therefore, the construction of a high precision sensitive high-frequency decision circuit is the major bottleneck in the construction of high-frequency synchronous sigma-delta modulators.